Typically, the design process for a new integrated circuit (IC) includes several steps using Electronic Design Automation (EDA) tools. During an initial schematic design of an (integrated) circuit, a designer identifies a set of functions to include in the initial schematic design, along with their standard delays. The designer uses computer implemented tools to perform functional simulation, to ensure that the design performs its intended function(s). Before the schematic design is laid out, the designer typically performs a pre-simulation. The pre-simulation takes into account device characteristics, to provide an estimate of circuit performance (e.g., performance in both analog and digital designs, including timing performance in digital designs). If the design meets circuit performance requirements in the pre-simulation, the designer initiates floorplan and layout phases, to generate an actual IC layout, using a place and route engine of the EDA tool. If the pre-simulation identifies significant performance issues, the designer modifies the design before proceeding to layout.
Following the layout process, the user verifies the design by using the EDA tools to perform design rule checks (DRC), layout versus schematic (LVS) checks, and RC extraction. In an example, the RC extraction tool takes into account the layout of the conductive (e.g., metal) lines of the interconnect layers generated by the router and computes parasitic resistance and capacitance elements associated with each conductive line. Subsequently, a post-simulation verifies circuit performance, taking into account the parasitic resistance and capacitance elements, in addition to the device characteristics.
With the advent of using advanced technology nodes having geometries of 40, 30, or 20 nanometers, or smaller, in a circuit, fluctuations in processing conditions (e.g., processing temperature, processing pressure, etc.) and/or environmentally conditions (e.g., a supplied voltage, an operating temperature) stochastically cause a variety of variations in device characteristics, which in turn changes the performance of the circuit. Thus, an EDA tool that considers the above-mentioned variations is needed.